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summit microelectronics, inc. ? 300 orchard city drive, suite 131 campbell, ca 95008 telephone 408-378- 6461 fax 408-378-6586 www.summitmicro.com 1 ? summit microelectronics, inc. 2000 2028 5.0 4/18/00 characteristics subject to change without notice summit microelectronics, inc. features ? precision voltage monitor ?v cc supply monitor - complementary reset outputs for complex microcontroller systems - integrated memory write lockout function - no external components required watchdog timer ? 1600 ms, internal two wire serial interface (i 2 c?) extended programmable functions available on sms24 high reliability ? endurance: 100,000 erase/write cycles ? data retention: 100 years 8-pin pdip or soic packages voltage supervisory circuit with watchdog timer sms2902/sms2904/sms2916 overview the sms29xx is a power supervisory circuit that monitors v cc and will generate complementary reset outputs. the reset pins also act as i/os and may be used for signal conditioning. the sms29xx also has an on-board watch- dog timer. the sms29xx integrates a nonvolatile serial memory. it features the industry standard i 2 c serial interface allowing quick implementation in an end-users? system. block diagram + ? gnd v cc 8 4 reset# 2 v trip reset control reset 7 1.26v scl 6 sda 5 watchdog timer wdi# 1 2028 t bd 2.0 write control nonvolatile memory array programmable reset pulse generator
2 sms2902/sms2904/sms2916 2028 5.0 4/18/00 pin configurations pin names symbol pin description wdi# 1 watchdog input /a high to low transition will clear the watchdog timer reset# 2 active low reset input/output nc 3 no connect, tie to ground or leave open gnd 4 analog and digital ground sda 5 serial memory input/ output data line scl 6 serial memory clock input reset 7 active high reset input/ output v cc 8 supply voltage 2028 pgm t1.1 figure 1. serial bus timing diagram capacitance t a = 25 c, f = 100khz symbol parameter max units c in input capacitance 5 pf l out output capacitance 8 pf 2028 pgm t2..0 scl sda in sda out t aa t r t h igh t low t su:sto t buf t su:dat t hd:dat t hd:sda t su:sda t dh 2028 ill5.0 t f wdi# reset# nc gnd v cc reset scl sda 1 2 3 4 8 7 6 5 8-pin pdip or 8-pin soic 2028 t pcon 2.0
sms2902/sms2904/sms2916 3 2028 5.0 4/18/00 absolute maximum ratings temperature under bias ......................................................................................................... ...................... -40 c to +85 c storage temperature ............................................................................................................ ......................... -65 c to +125 c soldering temperature (less than 10 seconds) ................................................................................... ................................ 300 c supply voltage ................................................................................................................. ............................................ 0 to 6.5v voltage on any pin ............................................................................................................. .......................... -0.3v to v cc +0.3v esd voltage (jedec method) ..................................................................................................... ..................................... 2,000v note: these are stress ratings only. appropriate conditions for operating these devices are given elsewhere in this specificati on. stresses beyond those listed here may permanently damage the part. prolonged exposure to maximum ratings may affect device reliability. 2.7v to 4.5v 4.5v to 5.5v symbol parameter conditions min max min max units f scl scl clock frequency 0 100 400 khz t low clock low period 4.7 1.3 s t high clock high period 4.0 0.6 s t buf bus free time before new transmission 4.7 1.3 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:sto stop condition setup time 4.7 0.6 s t aa clock to output scl low to sda data out valid 0.3 3.5 0.2 0.9 s t dh data out hold time scl low to sda data out change 0.3 0.2 s t r scl and sda rise time 1000 300 ns t f scl and sda fall time 300 300 ns t su:dat data in setup time 250 100 ns t hd:dat data in hold time 0 0 ns t i noise spike width noise suppression time constant 100 100 ns @ scl, sda inputs t wr write cycle time 10 10 ms ac electrical characteristics (over recommended operating conditions unless otherwise specified) 2028 pgm t5.0 2028 pgm t4.0 dc electrical characteristics (over recommended operating conditions unless otherwise specified) symbol parameter conditions min max units scl = cmos levels @ 100khz v cc =5.5v 3 ma i cc supply current (cmos) sda = open all other inputs = gnd or v cc v cc =3.3v 2 ma i sb standby current (cmos) scl = sda = v cc v cc =5.5v 50 a all other inputs = gnd i li input leakage v in = 0 to v cc 10 a i lo output leakage v out = 0 to v cc 10 a v il input low voltage s0, s1, s2, scl, sda, reset# 0.3xv cc v v ih input high voltage s0, s1, s2, scl, sda, reset 0.7xv cc v v ol output low voltage i ol = 3ma sda 0.4 v v cc =3.3v 25 a temperature min max commercial 0 c +70 c industrial -40 c +85 c recommended operating conditions 2028 pgm t3.0
4 sms2902/sms2904/sms2916 2028 5.0 4/18/00 figure 2. reset output timing reset circuit ac and dc electrical characteristics t a =-40 c to +85 c symbol parameter part no. min. typ. max. unit suffix v trip reset trip point a (or) blank 4.250 4.375 4.5 v b 4.50 4.625 4.75 v 2.7 2.55 2.65 2.75 v t purst reset timeout 200 ms t rpd v trip to reset output delay 5 s v rvalid reset output valid to v cc min. guarantee 1 v t glitch glitch reject pulse width note 1 30 ns v olrs reset output low voltage i ol = 1ma 0.4 v v ohrs reset high voltage output i oh = 800a v cc -.75 v v ulh v sense under-voltage threshold low to high 1.20 1.25 1.30 v v uhl v sense under-voltage threshold high to low 1.20 1.25 1.30 v v olh v sense over-voltage threshold low to high 1.20 1.25 1.30 v v ohl v sense over-voltage threshold high to low 1.20 1.25 1.30 v t vd1 delay to v low active 5 s t vd2 delay to v low released 5 s t wdto watchdog timeout period 1600 ms v cc v rvalid v trip t purst reset# reset 2028 t fig02 2.0 t glitch t rpd t purst t rpd
sms2902/sms2904/sms2916 5 2028 5.0 4/18/00 figure 3. watchdog timer timing diagram figure 4. reset reset reset reset reset as an input function t purst t purst reset (out) 2028 t fig04 2.0 reset# (in) reset# (out) t wdto t purst t wdto t purst t purst t wdto < t wdto 2028 t fig03 2.0 reset# reset# wdi# wdi#
6 sms2902/sms2904/sms2916 2028 5.0 4/18/00 endurance and data retention the sms29xx is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. it provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. reset controller description the sms29xx provides a precision reset controller that ensures correct system operation during brown-out and power-up/-down conditions. it is configured with two open drain reset outputs; pin 7 is an active high output and pin 2 is an active low output. during power-up, the reset outputs remain active until v cc reaches the v trip threshold and will continue driving the outputs for t purst (200 msec) after reaching v trip . the reset outputs will be valid so long as v cc is > 1.0v. during power-down, the reset outputs will begin driv- ing active when v cc falls below v trip . the reset pins are i/os; therefore, the sms29xx can act as a signal conditioning circuit for an externally applied reset. the inputs are edge triggered; that is, the reset input will initiate a reset timeout after detecting a low to high transition and the reset# input will initiate a reset timeout after detecting a high to low transition. refer to the applications information section for more details on device operation as a reset conditioning circuit. watchdog timer operation the sms29xx has a watchdog timer with a program- mable timeout period. whenever the watchdog times out it will generate a reset output on both reset# and reset. any transition on wdi will clear the watchdog timer. if a transition is not detected within t wdto seconds the watch- dog will time out and force the reset outputs active. pin descriptions serial clock (scl) - the scl input is used to clock data into and out of the device. in the write mode, data must remain stable while scl is high. in the read mode, data is clocked out on the falling edge of scl. serial data (sda) - the sda pin is a bidirectional pin used to transfer data into and out of the device. data may change only when scl is low, except start and stop conditions. it is an open-drain output and may be wire- ored with any number of open-drain or open-collector outputs. reset# - reset# is an active low output. whenever v cc is below v trip the sms29xx will drive the reset# pin to ground. the reset# pin is an i/o and can be used as a reset input. refer to figure 1 as an example use of this pin as a push button switch debounce circuit. it should be noted this is an open drain output and an external pull-up resistor tied to v cc is needed for proper operation. reset ? reset is an active high output. whenever v cc is below v trip the sms29xx will drive the reset pin to the v cc rail. the reset pin is an i/o and can be used as a reset input. it should be noted this is an open drain output and an external pull-down resistor tied to ground is needed for proper operation. wdi# - the wdi# input is used as a hardware method of clearing the watchdog timer. a high to low transition on this pin will clear the watchdog timer. if a transition is not detected within 1.6 seconds the watchdog will time out and force the reset outputs active.
sms2902/sms2904/sms2916 7 2028 5.0 4/18/00 figure 5. acknowledge response from receiver characteristics of the i 2 c bus general description the i 2 c bus was designed for two-way, two-line serial communication between different integrated circuits. the two lines are: a serial data line (sda), and a serial clock line (scl). the sda line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (see figure 1). data transfer between devices may be initiated with a start condition only when scl and sda are high (bus is not busy). input data protocol one data bit is transferred during each clock pulse. the data on the sda line must remain stable during clock high time, because changes on the data line while scl is high will be interpreted as start or stop condition. start and stop conditions when both the data and clock lines are high, the bus is said to be not busy. a high-to-low transition on the data line, while the clock is high, is defined as the ? start ? condition. a low-to-high transition on the data line, while the clock is high, is defined as the ? stop ? condi- tion . device operation the sms29xx is a 2k/4k/16k serial e 2 prom. the de- vice supports the i 2 c bidirectional data transmission protocol. the protocol defines any device that sends data onto the bus as a ? transmitter ? and any device which receives data as a ? receiver. ? the device controlling data transmission is called the ? master ? and the controlled device is called the ? slave. ? in all cases, the sms29xx will be a ? slave ? device, since it never initiates any data transfers. figure 6. slave address byte acknowledge (ack) acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either the master or the slave, will release the bus after transmit- ting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it re- ceived the eight bits of data (see figure 5). the sms29xx will respond with an acknowledge after recognition of a start condition and its slave address byte. if both the device and a write operation are selected, the sms29xx will respond with an acknowledge after the receipt of each subsequent 8-bit word. in the read mode, the sms29xx transmits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowledge is detected, and no stop condition is generated by the master, the sms29xx will continue to transmit data. if an acknowledge is not detected, the s ms29xx will terminate further data transmissions and awaits a stop condition before returning to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are the device type identifier ( ? 1010 ? ) (see figure 6). scl from master data output from transmitter data output from receiver start condition acknowledge t aa t aa 1 8 9 2028 ill7.0 1 0 1 0 r/w device identifier 2028 ill8.1 a 10 * a 8 ** a 9 * * = 2916 only ** = 2904 only
8 sms2902/sms2904/sms2916 2028 5.0 4/18/00 figure 7. page/byte write mode write operations the sms29xx allows two types of write operations: byte write and page write. the byte write operation writes a single byte during the nonvolatile write period (t wr ). the page write operation allows up to 16 bytes in the same page to be written during t wr . byte write upon receipt of both the slave address and word address, the sms29xx responds with an acknowledge for each. after receiving the next byte of data, it again responds with an acknowledge. the master then terminates the trans- fer by generating a stop condition, at which time the sms29xx begins the internal write cycle. while the internal write cycle is in progress, the sms29xx inputs are disabled, and the device will not respond to any requests from the master. refer to figure 7 for the address, acknowledge and data transfer sequence. page write the sms29xx is capable of a 16-byte page write opera- tion. it is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more bytes of data. after the receipt of each byte, the sms29xx will respond with an acknowledge. the sms29xx automatically increments the address for subsequent data words. after the receipt of each word, the low order address bits are internally incremented by one. the high order five bits of the address byte remain constant. should the master transmit more than 16 bytes, prior to generating the stop condition, the address counter will ? roll over, ? and the previously written data will be overwritten. as with the byte-write operation, all inputs are disabled during the internal write cycle. refer to figure 7 for the address, acknowledge and data transfer sequence. the next three bits are the high order address bits on the 2904 and 2916 and are ? don ? t care ? on the 2902. read/write bit the last bit of the data stream defines the operation to be performed. when set to ? 1, ? a read operation is selected; when set to ? 0, ? a write operation is selected. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 7 d 5 d 6 d 4 d 0 d 3 d 2 d 1 s t a r t word address data byte n data byte n+15 s t o p a c k acknowledges transmitted from sms29xx to master receiver slave address device type address read/write 0= write sda bus activity a c k a c k master sends read request to slave master writes word address to slave 1 0 1 0 0 data byte n+1 a c k master writes data to slave master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver shading denotes sms29xx sda output active master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver slave transmitter to master receiver master writes data to slave master writes data to slave acknowledges transmitted from sms29xx to master receiver if single byte-write only, stop bit issued here. x x r w a 10 a 9 a 10 a 9 a c k 2028 ill9.1
sms2902/sms2904/sms2916 9 2028 5.0 4/18/00 figure 9. current address byte read mode figure 8. acknowledge polling acknowledge polling when the sms29xx is performing an internal write operation, it will ignore any new start conditions. since the device will only return an acknowledge after it accepts the start, the part can be continuously queried until an acknowledge is issued, indicating that the internal write cycle is complete. to poll the device, give it a start condition, followed by a slave address for a write operation (see figure 8). read operations read operations are initiated with the r/w bit of the identification field set to ? 1. ? there are four different read options: 1. current address byte read 2. random address byte read 3. current address sequential read 4. random address sequential read current address byte read the sms29xx contains an internal address counter which maintains the address of the last word accessed, incremented by one. if the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. when the sms29xx receives the slave address field with the r/w bit set to ? 1, ? it issues an acknowledge and transmits the 8- bit word stored at address location n+1. the current address byte read operation only accesses a single byte of data. the master does not acknowledge the transfer, but does generate a stop condition. at this point, the sms29xx discontinues data transmission. see figure 9 for the address acknowledge and data transfer se- quence. issue start internal write cycle in progress; begin ack polling issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed with write issue stop await next command issue stop no no yes (internal write cycle is completed) yes 2028 ill10.0 s t a r t s t o p slave address device type address read/write 1= read sda bus activity d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 master sends read request to slave slave sends data to master master transmitter to slave receiver slave transmitter to master receiver 1 1 1 00 1 lack of ack (low) from master determines last data byte to be read 1 shading denotes sms29xx sda output active x x r w a c k x data byte 2028 ill11.1
10 sms2902/sms2904/sms2916 2028 5.0 4/18/00 figure 10. random address byte read mode random address byte read random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condi- tion and the slave address field (with the r/w bit set to write) followed by the address of the word it is to read. this procedure sets the internal address counter of the sms29xx to the desired address. after the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the r/w bit set to read. the sms29xx will respond with an acknowl- edge and then transmit the 8-data bits stored at the addressed location. at this point, the master does not acknowledge the transmission but does generate the stop condition. the sms29xx discontinues data transmission and reverts to its standby power mode. see figure 10 for the address, acknowledge and data transfer sequence. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 s t a r t word address s t o p a c k slave address slave address device type address read/write 0= write device type address sda bus activity s t a r t read/write 1= read a c k a c k master sends read request to slave master writes word address to slave master requests data from slave slave sends data to master 1010 1010 1 0 x x r w x a 9 x a 10 a 9 a 10 x r w xx lack of ack (low) from master determines last data byte to be read 1 slave transmitter to master receiver slave transmitter to master receiver shading denotes sms29xx sda output active slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver master transmitter to slave receiver slave transmitter to master receiver data byte 2028 ill12.1
sms2902/sms2904/sms2916 11 2028 5.0 4/18/00 sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read); however, the master now responds with an acknowledge, indicating that it requires additional data from the sms29xx. the sms29xx continues to output data for each acknowledge received. the master terminates the sequential read operation by not responding with an acknowledge, and issues a stop conditions. during a sequential read operation, the internal address counter is automatically incremented with each acknowl- edge signal. for read operations, all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address, the address counter will ? roll-over ? and the memory will continue to output data. see figure 11 for the address, acknowledge and data transfer sequence. figure 11. sequential read operation (starting with a random address read) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 shading denotes sms29xx sda output active s t a r t word address s t o p a c k acknowledges from sms29xx slave address slave address device type address read/write 0= write device type address sda bus activity s t a r t read/write 1= read x r w x acknowledge from master receiver a c k a c k a c k master sends read request to slave master writes word address to slave master requests data from slave slave sends data to master slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver 1010 1010 1 0 slave sends data to master x x r w a 10 a 9 a 10 a 9 x lack of ack (low) determines last data byte to be read 1 lack of acknowledge from master receiver slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver last data byte first data byte 2028 ill13.1
12 sms2902/sms2904/sms2916 2028 5.0 4/18/00 typical application configuration using system decode logic to reset wdi typical application using dual reset function and watchdog timer 5.0vdc wdi# reset# nc gnd v cc reset scl sda sms29xx i/o i/o z80 pb_rst# 2028 t fig13 2.0 rst# decoder 2028 t fig14 2.0 v cc wdi# reset# nc gnd v cc reset scl sda sms29xx 5.0vdc pbrst# tol gnd v cc st# rst# rst scl sda 24c16 i/o i/o ale 8051 family part ale 8051 family part rst i/o i/o 1232 gnd rst v cc = 3.0v or 5.0v wdi# reset# nc gnd v cc reset scl sda sms29xx reset# scl sda i 2 c peripheral rst scl (p0.0) sda (p0.1) ale 8051 type mcu pb_rst# 2028 t fig12 2.0 from this to this
sms2902/sms2904/sms2916 13 2028 5.0 4/18/00 .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic ill.2 8 pin soic (type s) package jedec (150 mil body width) 8 pin pdip (type p) package .375 (9.525) pin 1 indicator .015 (.381) min. .130 (3.302) .100 (2.54) typ. .018 (.457) typ. .060 .005 (1.524) .127 typ. .130 (3.302) seating plane .070 (1.778) .0375 (0.952) .300 (7.620) 5 -7 typ. (4 plcs) .350 (8.89) .009 .002 (.229 .051) 0 -15 .250 (6.350) 8pn pdip/p ill.3
14 sms2902/sms2904/sms2916 2028 5.0 4/18/00 notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect it s safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives writte n assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. i 2 c is a trademark of philips corporation. ? copyright 2000 summit microelectronics, inc. ordering information sms2902 p a base part number v trip package p = pdip s = soic a = 4.5v b = 4.75v 2.7 = 2.7v blank = 4.5v 2028-02 tree 2.0 sms2904 p a base part number v trip package p = pdip s = soic a = 4.5v b = 4.75v 2.7 = 2.7v blank = 4.5v 2028-04 tree 2.0 sms2916 p a base part number v trip package p = pdip s = soic a = 4.5v b = 4.75v 2.7 = 2.7v blank = 4.5v 2028-16 tree 2.0

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